Conventional devices such as microprocessors and graphics processors that are used in high-performance digital systems may have varying current demands based on the processing workload. For example, current demands may increase dramatically when a block of logic is restarted after a stall or when a new request initiates a large computation such as the generation of a new image. Conversely, current demands may decrease dramatically when a block of logic becomes idle. When the current demand increases and sufficient power is not available, the supply voltage that is provided to the device may drop below a critical voltage level, potentially causing the device to fail to function properly. When the current demand decreases and the supply voltage that is provided to the device rises above a critical voltage level, circuits within the device may fail to function properly and may even be destroyed.
A conventional mufti-phase switching regulator is an electric power conversion device that interfaces between a power supply and a device, providing current to the device and responding to changes in current demands to maintain a supply voltage level. However, a conventional multi-phase switching regulator relies on a large inductor for voltage conversion and the large inductor limits the ability of the conventional multi-phase switching regulator to quickly respond to dramatic changes in current demands (i.e., current transients). A typical 30 A phase of the conventional multi-phase switching regulator may use a 0.5 μH inductor for voltage conversion. The current response is limited to di/dt=V/L which for V=11V (dropping a 12V input to a 1V supply voltage level) and L=0.5 μH gives 22 A/μs. Increasing the current provided to a device by 10 A in would require at least 500 ns. Additionally, synchronization of the pulse width modulation switching operation may increase the current response time of the conventional multi-phase switching regulator by several microseconds. When a clock period of the device is less than the current response time, the device may fail to function properly. A 500 MHz dock has a period of 2 ns, so hundreds of clock periods may occur during a 500 ns current response time.
Thus, there is a need for improving regulation of voltage levels and/or other issues associated with the prior art.